Thesis Title:
Multi-Domain Coincidence Processing and Memory Architecture for Real-Time Geiger Mode LiDAR
My thesis research concerns the data processing for Geiger-Mode aerial LiDAR sensors, which are single photon-sensitive imaging arrays capable of capturing multiple gigabytes of range data per second. They measure the round-trip time for laser pulses by reverse-biasing photosensitive diodes close to breakdown, allowing incoming photons to cause avalanche breakdown that is detectable directly in the digital domain without analog-to-digital conversion. The drawback of this (in comparison to linear LiDAR) is that spurious inputs, foliage, and other unwanted data must be filtered out before a useable terrain map, represented as a 3D point cloud, can be rendered.
This requires something called coincidence processing, the essential goal of which is to find the coincident range returns, or the modes, of the data. Coincidence processing involves generating and updating a dense, multi-dimensional histogram accurately registered in 3D space, and then using tunable filters to identify the peaks of the histograms. While conceptually simple, this becomes a difficult problem in practice due to the massive data rate and the difficulty of accurately coordinating the sensor view from a moving aerial platform.
This arduous problem is currently handled by either saving the data as a time-correlated stream for later processing on the ground, or by racks of servers consuming kilowatts of power that need to be carried onboard. Obviously, that limits implementation to rather large aircraft.
My solution to this uses a Xilinx System-on-Chip [SoC] which includes several ARM CPUs and a tightly coupled flexible FPGA logic fabric. The majority of the trouble lies in designing a memory architecture that can deal with the data rate and the read-modify-write nature of histogram generation, necessitating multiple levels of buffering and simultaneous pipelined processing in several domains of physical space. Motion and orientation compensation are critical in every aspect of this design. Also included in the design is a DDR4 memory coupled directly to the logic fabric that is used to store the level-two histogram
The counting, histogram generation, and peak-detecting filter logic was all implemented in the FPGA using System Verilog HDL code. Higher-level management and some aspects of the motion compensation are handled by the real-time processor on the SoC. From the FPGA output, the peaks are read by the main CPU via an AXI4 buffer and some post-processing is applied to re-contextualize the point locations in 3D space. For now, these are directly printed for debugging, but future designs based on this would use the CPU to manage a local 3D point cloud that can be further filtered and read out to operators on the ground.
This button downloads a PowerPoint presentation containing graphics I made for understanding the problem, system design, concept of operations, and coordinate transform mathematics